1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a wordline driver suitable for a merged bank architecture (MBA).
2. Background of the Related Art
As SDRAM has become highly integrated, it is essential to have a merged bank architecture (MBA) in which a memory chip is divided into a plurality of banks systems each of which has at least 4 banks, and an X-address predecoder or a control block is commonly owned by each divided banks. In this manner, an optimum size of the memory chip can be achieved.
An X-address predecoder (not shown) decodes an external address (i.e., X-address) in accordance with an active command to output a decoding signal. That is, for a 12 bit X-address B0-B11, the X-address predecoder outputs an upper coding signal XP1 by decoding bits B8-B11, an intermediate coding signal XP2 by decoding bits B5-B7, and a lower coding signal XP3 by decoding bits B0-B4.
FIG. 1 is a circuit diagram of a related art global wordline driver. As shown in FIG. 1, each of PMOS transistors PM1, PM2 serves as a switch for supplying a boosted voltage Vpp. The PMOS transistor PM1 and an inverter IN1 latch a disabled state of a global wordline. Each of NMOS transistors NM1, NM3 sets/resets the global wordline driver, and each of a PMOS transistor PM2 and a NMOS transistor NM2 drives the global wordline.
The operation of the related art global wordline driver will now be described. First, when the active command is inputted and the X-address predecoder (not shown) is set, the X-address predecoder decodes an inputted X-address and outputs upper, intermediate, and lower coding signals XP1, XP2, XP3, which are at low, low, and high levels, respectively. As a result, the NMOS transistor NM1 is turned on according to the lower coding signal XP3. Thus, a voltage of a node A becomes a Vss level and a voltage of a node B becomes a Vpp level. The NMOS transistor NM2 is turned on by the B node voltage at the Vpp level, and a global wordline signal GWLB becomes enabled at a low level.
Next, when a precharge command is inputted, the X-address predecoder (not shown) is reset. In this case, the upper, intermediate, and lower coding signals XP1, XP2, XP3 from the X-address predecoder become high, high, and low levels, respectively.
Accordingly, the NMOS transistor NM1 is turned off and the NMOS transistor NM3 is turned on. The PMOS transistor PM2 is turned on by the voltage of the node B at the Vss level, and thus the global wordline signal GWLB becomes disabled. Further, the disabled state of the global wordline is latched by the PMOS transistor PM1 and the inverter IN1. Thus, the related art global wordline driver drives the global wordline and latches the disabled state of the global wordline in accordance with set/reset operations of the NMOS transistor NM1 or the NMOS transistor NM3.
As described above, the related art global wordline driver has various disadvantages. There is no unit for latching an enabled state of the global wordline in the global wordline driver itself. Accordingly, when the global wordline is enabled, the coding signal from the X-address predecoder (not shown) can not be continuously applied thereto. Thus, the related art global wordline driver is not suitable for a semiconductor device such as an MBA in which the X-address predecoder is commonly owned.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.